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This is my project for the 74xx contest. It’s a 4-bit SAR ADC.

An ADC, which stands for Analog to Digital Converter, is a circuit that converts an analog value into a digital representation in binary form. Each bit of the result has a weight. The 0th bit is the LSB and its weight is Vref/2^N where Vref is the reference voltage of the converter and N is the number of bits. In my case Vref = 5V and N = 4 so the LSB = 0.3125V. The ADC output is then given by (Input value)/LSB.

There are various ADC architectures (flash, SAR, Sigma-Delta), each one with its pros and cons. The SAR (Successive approximations) works by comparing the analog value to be converted with a generated value with a method similar to the mathematical bisection method. More precisely, it starts comparing, by a simple difference, the input value with Vref/2 (it divides the full range Vref in two halves); if the result is > 0 the N-bit (called MSB) = 1, i.e. the input value is greater than Vref/2, otherwise N-bit = 0. Now it divides the “new range”, upper or lower half of Vref, in two halves by setting the (N-1)-bit = 1, keeping the previous N-bit, and it compares this value with the input voltage. If the result > 0 then (N-1)-bit = 1, otherwise (N-1)-bit = 0. It then goes on with the (N-2)-bit and so forth to the LSB. The conversion time is, at best, Tck*N. The generated value for the comparison is digital, so a DAC is needed to do the comparison with the analog input value.

Here is a block schematic of the general circuit.

The flip-flops are used as a shift register. It starts with Φ0 feeding the DAC with digital value 1000. The output of the amplifier is 0 or 1 if In > DAC and vice-versa, respectively. At the next clock pulse, the flip-flop 1 (FF1) stores the value of the amplifier, and we are in Φ1. The DAC is fed with (FF1 value)100. At the next clock pulse FF2 stores the value of the FF1 (the value of FF1 is shifted and this is why is called shift register) and FF1 stores the value of the amplifier and we are in Φ2. The same happens for Φ3. Now the N-bit (MSB) is in the FF3, (N-1)bit in FF2 and (N-2)bit in FF1. The output of the amplifier gives the last bit (LSB). At the clock pulse FF4 saves FF3 content, FF3 saves FF2, FF2 saves FF1 and FF1 saves the LSB. During this time the RC of the RST signal is charging. When it reaches the threshold value of the RST pin of the counter, it is reset and the DEMUX brings us back to Φ0. The sample&hold samples the input value, CK_OUT signal goes high and the output buffer saves the content of the FFs. The RC of the CK_OUT signal starts to charge and its waveform (exponential) is squared by the inverters to give the TRIGGER signal. This delay is needed to give the output buffer the time to store its input values before any circuits can read them. Since Φ4 went 0 the RC of the RST signal is discharging. When under threshold, causes the reset phase to stop and a new conversion can start. The RC of the RST signal is needed to comply with the set-up and hold times of the ICs of the whole loop (from RST to RST) and also by comply to the set-up and hold time of the FFs. Finally the DAC is implemented by the simple R-2R configuration.

Here is the signal diagram of the clock and phases.

Here is the circuit schematic.

schematic

– the T1 is needed because the output of the amplifier goes from -9V and +9V and needs to be converted from 0 to 5V. The amplifier input must then be inverted because the T1 insert an inversion.

– the RC right after T1 is needed to delay the signal and comply with the hold times of the flip-flop

– the CMOS inverters at the 74241N output are needed because this chip has an ugly darlington output which means an unacceptable ~1.4V drop on the output

– the hold capacitance on the amplifier inverting input gives the limit on the lower working frequency due to the amplifier input impedance

– the maximum working frequency is approximately given by the longest RC i.e. the path from the FF out to the same FF input passing through the tristate buffer, the amplifier, the T1 and its RC, plus the set-up time of the FF. Its in the order of 10kHz. But we have to keep in mind what happens on reset. The phase diagram shows that after reset the Φ0 could have less than one clock period, so this is the limiting case approx. 5kHz assuming the worst case when RST phase spans half clock period.

A photo and a video of the breadboarded circuit:

Cpu86